Open Positions.

We are not hiring for roles. We are assembling a team to change the axiom. Ten current openings across four disciplines.

Primary location is Riyadh, Kingdom of Saudi Arabia, unless noted. Relocation support is available for key hires. To apply, send a brief introduction and your most relevant work to careers@aternaworld.com.

Role 1

Senior Research Scientist — Lie-Algebraic Computation

Discipline Research
Location Riyadh, KSA
Type Full-time
Summary — Advance the mathematical core of FIL — formalizing Lie-algebraic structures into computational logic that can be verified and implemented in silicon.

What you'll do

  • Develop and formalize the Lie-algebraic foundations underlying FIL's 31-state cycle.
  • Translate abstract algebraic structures into specifications consumable by RTL and verification teams.
  • Publish internal proofs and contribute to the patent portfolio.
  • Collaborate with hardware engineers to ensure mathematical fidelity in implementation.

What we're looking for

  • PhD in mathematics, theoretical computer science, or a closely related field.
  • Deep knowledge of Lie groups, Lie algebras, and representation theory.
  • Familiarity with formal methods and proof assistants is a strong advantage.
  • Ability to communicate rigorous mathematics to engineering teams.

Role 2

Formal Verification Engineer

Discipline Research
Location Riyadh, KSA/Remote
Type Full-time
Summary — Prove that FIL-native circuits do exactly what the mathematics says — no more, no less. What you'll do
  • Build formal verification flows for FIL/GLU logic against algebraic specifications.
  • Develop proof harnesses comparing FIL circuits to binary-gate equivalents.
  • Define coverage and correctness criteria for tape-out readiness.
  • Partner with research and RTL teams to close specification gaps.

What we're looking for

  • Strong background in formal verification, model checking, or theorem proving.
  • Experience with SystemVerilog Assertions, or proof assistants (Coq, Lean, Isabelle).
  • Understanding of digital logic and RTL design.
  • Rigorous, detail-driven engineering discipline.

Role 3

Post-Quantum Cryptography Researcher

Discipline Research
Location Riyadh, KSA
Type Full-time
Summary — Connect FIL's structural quantum resilience to the world's emerging PQC standards.

What you'll do

  • Analyze FIL's gate-level resistance to Shor-class attacks and document the security argument.
  • Map the architecture to NIST SP 800-208 and FIPS 203/204/205.
  • Advise on hardware-level cryptographic conformance for sovereign deployments.
  • Engage with government security teams under NDA.

What we're looking for

  • Graduate degree in cryptography, mathematics, or security engineering.
  • Working knowledge of lattice-based cryptography and the NIST PQC standards.
  • Understanding of side-channel and implementation security.
  • Ability to translate cryptographic theory into hardware requirements.

Role 4

Senior RTL Design Engineer

Discipline Hardware Engineering
Location Riyadh, KSA
Type Full-time
Summary — Turn FIL algebra into register-transfer-level designs that become the GLU.

What you'll do

  • Design and implement RTL for FIL-native compute blocks (GLU).
  • Optimize for power, performance, and area against binary baselines.
  • Work with verification to reach formal sign-off.
  • Prepare designs for FPGA prototyping and ASIC implementation.

What we're looking for

  • Strong Verilog / SystemVerilog RTL design experience.
  • Track record taking designs from specification to silicon or FPGA.
  • Understanding of low-power design techniques.
  • Comfort working from non-standard (algebraic) specifications.

Role 5

FPGA Engineer — Bring-Up & Validation

Discipline Hardware Engineering
Location Riyadh, KSA / Kansas, USA
Type Full-time
Summary — Own the FPGA platform where FIL silicon is validated before tape-out.

What you'll do

  • Bring up FIL/GLU designs on Xilinx Ultrascale+ and similar fabrics.
  • Build benchmark and power-measurement harnesses for validation.
  • Triage hardware/software integration issues during bring-up.
  • Document validation results for partner review.

What we're looking for

  • Hands-on FPGA bring-up and debug experience.
  • Familiarity with high-speed interfaces (PCIe) and lab instrumentation.
  • Scripting for automated test (Python preferred).
  • Methodical approach to hardware debugging.

Role 6

ASIC Physical Design Engineer

Discipline Hardware Engineering
Location Kansas, USA
Type Full-time
Summary — Drive the 5nm FIL-ASIC from netlist to tape-out under ITAR-compliant protocols.

What you'll do

  • Own floorplanning, place-and-route, timing closure, and signoff for the FIL-ASIC.
  • Manage power, IR-drop, and physical verification (DRC/LVS).
  • Coordinate with the foundry and packaging partners.
  • Operate within ITAR-controlled technology handling procedures.

What we're looking for

  • Proven ASIC physical design experience at advanced nodes (≤7nm preferred).
  • Mastery of industry PnR and signoff toolchains.
  • Strong timing and power closure track record.
  • Eligibility to work with ITAR-controlled technology.

Role 7

Hardware Security Architect

Discipline Hardware Engineering
Location Riyadh, KSA
Type Full-time
Summary — Design the security properties that make Aterna hardware fit for high-threat sovereign deployment.

What you'll do

  • Define hardware security architecture, including tamper-evidence and secure boot.
  • Drive air-gap deployability and side-channel resistance.
  • Support audit and certification for sovereign partners.
  • Collaborate with the PQC research team on cryptographic integrity.

What we're looking for

  • Experience in hardware security architecture or secure silicon design.
  • Knowledge of side-channel attacks, secure boot, and key management.
  • Familiarity with security certification regimes.
  • Threat-modelling discipline for critical infrastructure.

Role 8

Compiler & eABI Toolchain Engineer

Discipline Software Engineering
Location Riyadh, KSA / Remote
Type Full-time
Summary — Build the eABI translation layer that lets existing code run on FIL hardware untouched.

What you'll do

  • Develop the eABI layer translating standard ABI calls to GLU instruction sequences.
  • Optimize instruction dispatch algebraically for performance.
  • Maintain C++/Rust toolchain integration and bindings.
  • Profile and tune the host-to-accelerator path.

What we're looking for

  • Strong systems programming in C++ and/or Rust.
  • Compiler, ABI, or toolchain engineering experience.
  • Understanding of accelerator programming models.
  • Performance-engineering mindset.

Role 9

ML Framework Integration Engineer

Discipline Software Engineering
Location Riyadh, KSA
Type Full-time
Summary — Make popular ML frameworks run on Aterna hardware with no surprises for data scientists.

What you'll do

  • Integrate ML frameworks (PyTorch-class) with the G1 accelerator via eABI.
  • Build and maintain inference pipelines and example workloads.
  • Benchmark model performance and energy efficiency.
  • Support partner deployments of AI inference workloads.

What we're looking for

  • Strong Python and C++ engineering.
  • Experience integrating or optimizing ML frameworks.
  • Understanding of inference performance and accelerator offload.
  • Clear documentation and developer-experience instincts.

Role 10

Sovereign Solutions Architect

Discipline Systems & Deployment
Location Riyadh, KSA
Type Full-time
Summary — Translate FIL hardware into deployable sovereign cloud, critical infrastructure, and edge systems.

What you'll do

  • Design reference architectures integrating Aterna hardware into partner environments.
  • Lead technical discovery and pilot deployments with sovereign partners.
  • Coordinate hardware-software integration and security certification.
  • Act as the technical bridge between partners and engineering.

What we're looking for

  • Solutions or systems architecture experience at enterprise/government scale.
  • Understanding of data-center, cloud, or critical-infrastructure deployments.
  • Excellent communication with technical and executive stakeholders.
  • Comfort operating under NDA and compliance constraints.