Straight answers about the technology, the hardware, sovereignty, security, and working with Aterna.
FIL is an algebraic computation framework built on Lie group theory. Instead of encoding information as discrete 0/1 states, it operates on a closed 31-state algebraic cycle, carrying far greater information density per cycle than binary logic.
FIL is not multi-valued logic — it does not simply add voltage levels to binary gates. It is also not quantum computing: every FIL computation is exact, deterministic, and algebraically verifiable. FIL is a new computational axiom, not an extension of the old one.
The 96% figure is a gate-level reduction versus equivalent binary CMOS gates, validated through FPGA emulation, RTL simulation with formal verification, and independent power measurement on G1 Alpha cards. At system level the net reduction is approximately 70–80%. Full methodology is available under NDA.
The G1 is an industrial-grade PCIe Gen5 acceleration card running FIL/GLU logic at a 180W power envelope. It is designed for immediate deployment in sovereign data centers.
No. The eABI (extended Application Binary Interface) is a transparent translation layer. Existing Python, C++, and Rust code runs without recompilation or re-architecture.
The 96% figure is a gate-level reduction versus equivalent binary CMOS gates, validated through FPGA emulation, RTL simulation with formal verification, and independent power measurement on G1 Alpha cards. At system level the net reduction is approximately 70–80%. Full methodology is available under NDA.
Aterna owns its architecture (FIL and GLU are original IP with no x86/ARM/RISC-V dependency), targets manufacturing within a trusted, auditable supply chain, builds cryptographic integrity into the hardware, and develops domestic human capital through the Aterna Academy.
Initial production runs at an ITAR-compliant facility in the United States. From 2028, a manufacturing bridge transfers capability to facilities within the Kingdom of Saudi Arabia.
Because FIL operates on Lie-algebraic state spaces rather than discrete binary integers, it is structurally resistant to Shor-class attacks at the gate level. Post-quantum resilience is a property of the mathematics, not a software layer bolted on afterwards.
Aterna's posture aligns with NIST SP 800-208 and FIPS 203/204/205 (ML-KEM, ML-DSA, SLH-DSA). The architecture does not replace these standards; it provides a hardware substrate that makes them structurally stronger.
Qualified technical, commercial, investment, and sovereign partners, under an executed NDA and — where controlled technology is involved — the relevant export-control authorizations.
Through the secure government channel (government@aternaworld.com) for classified briefings, architecture reviews, and pilot deployment discussions, all under NDA.
Both. Aterna serves sovereign governments and enterprise partners operating critical infrastructure, energy, sovereign cloud, and edge environments.
Yes — across research, hardware engineering, software engineering, and systems & deployment, primarily in Riyadh with engineering presence linked to the US manufacturing program. See the Careers page or write to careers@aternaworld.com.
Press: press@aternaworld.com. Investors: investors@aternaworld.com or the Investor Portal. General enquiries: hello@aternaworld.com.
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